1. Field of the Invention
The present invention relates to a PLL circuit in a PLL synthesizer which utilizes a pulse swallow system. More specifically, the invention relates to a PLL circuit which prevents the module from being erroneously operated in a PLL circuit.
2. Description of the Related Art
A PLL circuit has heretofore been known that carries out the PLL operation by using the pulse swallow-type prescaler system.
In the field of mobile body communications in recent years, there is a trend to expand the frequency band used for such communications, necessitating the employment of high-speed tuning.
In order to realize such high-speed tuning, it becomes necessary to increase a reference frequency resulting, however, in a delay of operation of the PLL circuit and the circuit constituting the periphery thereof and also in the occurrence of error in the PLL operation. It has therefore been urged to solve such problems.
In order to solve the problem of delay, it is necessary to shorten as much as possible the delay time of the elements which comprise the PLL circuit and also the circuits forming the periphery thereof. In the conventional PLL synthesizers of this type, however, the delay time can be shortened by using, for example, a high-speed device or a device of a large power.
In the conventional PLL synthesizers, the delay time in the devices is shortened by using a device that operates at a high speed or by using a device of a large power which has a large size, resulting in an increase in the consumption of electric power and the size of the circuit, causing the cost to be increased. In the modern mobile body communications devices powered by cells, in particular, an increase in the consumption of electric power becomes a fatal defect which makes it difficult to solve the problem from a practical point of view.
In the conventional PLL circuit, therefore, it was not possible to avoid the occurrence of an erroneous operation caused by the delay of a signal MO that controls the module operation when a high frequency is used.
That is, when a PLL circuit for a synthesizer is constituted relying upon the conventional pulse swallow-type prescaler system, there is employed a circuit structure having a block diagram as shown in, for example, FIG. 7.
That is, in the synthesizer of the pulse swallow-type prescaler system which includes a prescaler circuit 1 and a PLL circuit 2, the PLL circuit is provided with a PLL COUNTER CIRCUIT 7, and the prescaler circuit 1 is provided with a counter 3 that performs module operation, an extender circuit 4 and an OR gate circuit 6 which generates a module control signal MO to control the module operation of the counter unit 3.
That is, in the above-mentioned conventional PLL circuit, the OR gate circuit 6 finds an OR logic based on a module pulse signal (b) from the PLL COUNTER circuit 7 and an internal clock signal (f) from the extender circuit 4, and outputs a module control signal MO to control the module operation of the counter 3. However, when a delay exists between the module pulse signal (b) and the internal clock signal (f) from the extender circuit 4, an erroneous operation takes place temporarily in the generation of the module control signal MO. Therefore, the module does not properly operate in the counting unit, and a predetermined frequency-dividing operation is not executed.
One of the causes of the generation of such an erroneous operation is attributed to the fact that in finding an OR logic based on the module pulse signal (b) from the PLL COUNTER circuit 7 and the internal clock signal (f) from the extender circuit 4, the logic is determined by detecting the rising edge or the falling edge of the module pulse signal (b). Therefore, when the waveform of the pulse signal that is rising or falling is deformed, or when the rising or falling timing of the pulse is deviated due to the delay, the module control signal MO is not properly generated and an error develops in the module operation.
The above condition will now be described with reference to FIGS. 8 and 9.
FIG. 8 illustrates the concrete circuit structure of the counter 3 and the extender circuit 4 of the prescaler circuit 1 in the conventional PLL circuit, and wherein the counter 3 is comprised of flip-flops FF1 to FF3 of the edge trigger type and OR gates 9 and 10, and wherein the flip-flop FF3 has a reset terminal M.
The extender circuit 4 is comprised of, for example, T-type flip-flops T-FF4 and T-FF5, and a frequency-dividing ratio is determined by the number of stages of the T-type flip-flops T-FF.
The output of the extender circuit 4, i.e., the Q-output (a) of the T-type flip-flop T-FF5, is output, for example, to the PLL circuit 2 (FIG. 7) via an inverter 11 to drive the PLL COUNTER circuit 7.
The module pulse signal MD output from the PLL circuit 2 and the Q-outputs from the T-type flip-flops T-FF4 and T-FF5 of the extender circuit 4 are input to the OR gate 12, and an output of "L" level is produced from the OR gate 12 when the inputs are all of the "L" level. The output of the "L" level is input to the reset terminal M of the flip-flop FF3 in the counter 3. Therefore, an output of the "H" level, from the Q-terminal of the flip-flop FF3, is input to the D-terminal of the flip-flop FF1 via the OR gate 9 in the counter unit 3. Accordingly, the Q-bar output of the flip-flop FF1 changes, by being deviated by one pulse, with respect to the input clock signal. Therefore, the counter 3 executes a module operation in which a frequency-dividing ratio P+1 is selected with respect to a predetermined frequency-dividing ratio P.
FIG. 9 is a diagram of waveforms illustrating the driving conditions of the devices of a PLL circuit having the circuit structure shown in FIG. 8, and illustrates the case where the module operations of dividing the frequency by 16 (P) and dividing the frequency by 17 (P+1) are alternately repeated in the prescaler circuit at the input frequency f.sub.vco.
In the PLL circuit of the pulse swallow-type prescaler system, as in the present invention, a value obtained by dividing a quartz oscillation frequency f.sub.osc by a frequency-dividing ratio R of a reference counter is used as a reference frequency fr (fr=f.sub.osc .div.R) and an oscillation frequency of a VCO oscillator provided in the PLL circuit is denoted as f.sub.vco. Then, a comparison frequency fp to be compared with the reference frequency fr is expressed as fp=f.sub.vco .div.(P.times.N+A). In the prescaler circuit, the VCO oscillation frequency f.sub.vco is used as an input frequency.
Here, P denotes the frequency-dividing ratio of the prescaler, N denotes the frequency-dividing ratio of a comparator counter which is a main counter in the PLL circuit, and A denotes the frequency-dividing ratio of the pulse swallow counter.
When the PLL loop is locked, fr=fp from the characteristics of the PLL circuit, and a relationship f.sub.osc .div.R=f.sub.vco .div.(P.times.N+A) holds.
When the reference frequency is increased in order to accomplish high-speed tuning, as mentioned earlier, the frequency-dividing ratio R of the reference counter becomes small and it inevitably becomes necessary to decrease the relationship P.times.N+A.
However, conditions P&lt;N and A&lt;N exist. Therefore, P must be decreased if it is attempted to decrease N.
When the frequency-dividing ratio of the prescaler is decreased under such circumstances, the frequency input to the comparator counter, which is the main counter, becomes very great and, as a result, the operation processing time in the comparator counter is not sufficient to match the processing time in the prescaler circuit unit. Therefore, the module pulse signal MD output from the PLL circuit unit is delayed, causing the module to erroneously operate in the counting unit. For instance, the frequency is divided by 16 though the frequency should have been divided by 17. Accordingly, the predetermined frequency-dividing ratio is not correctly obtained.
Such a condition will now be described with reference to the waveform diagram of FIG. 9. A pulse signal IN (or IN-bar) having an input frequency f.sub.vco is input to a corresponding input of the OR gate 10 of the counter 3, a signal that turns "H" and "L" after every two input pulse signals IN or IN-bar is output from the Q-bar terminal of the flip-flop FF1 of the counter unit 3, and a pulse signal that turns "H" and "L" at the same timing but delayed by one pulse behind the Q-bar output of the flip-flop FF1 is output from the Q-terminal of the flip-flop FF2 of the counter 3.
The flip-flop FF3 of the counter 3 is usually maintained in a reset condition. Therefore, a signal Q3 of "L" level is usually output from the Q-terminal of the flip-flop FF3 and is input to the D-terminal of the flip-flop FF1 together with the output Q2 from the Q-terminal of the flip-flop FF2 via the OR gate 9.
The flip-flop FF3 is released from the reset condition as the module control signal MO of "L" level output from the OR gate 12 is input to the reset terminal M of the flip-flop FF3 as will be described later.
In the extender circuit 4, furthermore, a signal Q1-bar output from the Q-bar terminal of the flip-flop FF1 of the counter 3 is input to a clock terminal C of the T-type flip-flop T-FF4, a pulse signal Q4 of a period twice as great as the frequency of the Q1-bar signal is output from the Q-output terminal thereof and is input to a clock terminal C of the neighboring T-type flip-flop T-FF5, and a pulse signal Q5 of a period twice as great as the frequency of the signal Q4 is output from the Q-output terminal of T-FF5 and is input as an output OUT of the extender unit 4 to the PLL circuit element 7 of the PLL circuit 2 via the inverter 11.
The D-input terminal and the Q-bar output terminal of each of the T-type flip-flops T-FF4 and T-FF5 are connected together.
Therefore, the period of the signal OUT output from the extender circuit 4 represents the period derived by dividing the frequency by 16 in the prescaler circuit 1.
Under such a condition, while an output signal pulse, representing a period derived by dividing the frequency by 16 and output by the prescaler circuit 1, is input to the PLL COUNTER circuit 7, a module pulse signal MD, having a logic level that instructs the division of frequency by 16, is output from the PLL COUNTER circuit 7--i.e., the signal MD of "H" level is output from the PLL COUNTER circuit 7. Here, however, a module pulse signal MD, having a logic level that instructs the division of frequency by 17, is output--e.g., the signal MD of "L" level is output--at the moment when the period of the output signal pulse, instructing the period derived by dividing the frequency by 16 output by the prescaler circuit unit 1, is terminated.
A module control signal MO is maintained usually at the "H" level. During this period, the flip-flop FF3 is maintained reset, and then a module control signal of "L" level is output from the OR gate 12 at the moment when the signals input to the OR gate 12 all assume the "L" level. The module control signal of "L" level is then input to the reset terminal M of the flip-flop FF3, whereby the flip-flop FF3 is released from the reset condition, and a signal Q3 of the "H" level is output from the Q-terminal of the flip-flop FF3.
According to the above-described prior art, when the output of the module pulse signal MD changes at a delayed timing or when the waveform of edge of the module pulse signal MD mildly changes as designated at (Z), the timing at which the control signal MO for controlling the modulating operation of the counter 3 is output, is overlapped with the timing at which the data input to all of the input terminals of the OR gate circuit re changed to "L" level.
In this case, however, the waveform of the output signal of the module controlling signal is disturbed (X) and accordingly, it adversely affects the waveform of the output signal Q3 output from the Q-terminal of the flip-flop FF3, and having "H" level signal to make it difficult to form a proper pulse waveform as designated at (Y).
When such a condition develops, the signal output from the Q-bar terminal of the flip-flop FF1 is continuously output, maintaining the "L" level for one more additional reference pulse that is input due to the signal Q3 of "H" level output from the Q-terminal of the flip-flop FF3, and the frequency is divided by 17. Under the above-mentioned condition, however, a pulse of the correct "H" level is not input to the D-terminal of the flip-flop FF1. Accordingly, division of the frequency by 17 is not executed at pulse positions designated at W1 to W5 in FIG. 9. That is, division of the frequency by only 16 is executed despite the module operation being carried out. Accordingly, the desired division of the frequency by 16 and division of the frequency by 17 are not alternately executed during the module operation, and division by 16 only is repetitively executed.